A 0.18-/spl mu/m CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter

A DCS1800 offset-phase-locked-loop upconversion modulation loop integrated circuit (IC) fabricated in a 0.18-/spl mu/m CMOS technology is presented in this paper. This IC operates at 2.8-V supply voltage with a current consumption of 36 mA. The measured root-mean-square and peak phase errors of the Gaussian minimum shift keying (GMSK) transmission signal are 1.6/spl deg/ and 4/spl deg/, respectively. It is shown that such circuits can be implemented in CMOS process with current dissipation and performance comparable to BiCMOS chips. Advantages of upconversion modulation loop and design issues of I/Q modulators are also described.

[1]  Asad A. Abidi,et al.  A single-chip 900-MHz spread-spectrum wireless transceiver in 1-/spl mu/m CMOS. I. Architecture and transmitter design , 1998 .

[2]  Jieh-Tsorng Wu,et al.  A 2 V 100 MHz CMOS vector modulator , 1997 .

[3]  Taizo Yamawaki,et al.  A CMOS Offset Phase Locked Loop for a GSM Transmitter , 1999 .

[4]  H. Notani,et al.  A 622-MHz CMOS phase-locked loop with precharge-type phase frequency detector , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[5]  M.A. Margarit,et al.  A low power high spectral purity frequency translational loop for wireless applications , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[6]  J. Fenk,et al.  An up-conversion loop transmitter IC for digital mobile telephones , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[7]  V. Thomas,et al.  A bipolar upconversion modulation loop transmitter for dual-band mobile communications , 1998, 1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192).

[8]  M. Steyaert,et al.  A 2-V CMOS cellular transceiver front-end , 2000, IEEE Journal of Solid-State Circuits.

[9]  M. Ingels,et al.  A fully-integrated single-chip SOC for Bluetooth , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[10]  Kyoohyun Lim,et al.  A low-noise phase-locked loop design by loop bandwidth optimization , 2000, IEEE Journal of Solid-State Circuits.

[11]  Behzad Razavi,et al.  RF transmitter architectures and circuits , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[12]  Qiuting Huang,et al.  A 20-mA-receive, 55-mA-transmit, single-chip GSM transceiver in 0.25-μm CMOS , 1999, IEEE J. Solid State Circuits.

[13]  T. Endo,et al.  A 2.7 V GSM RF transceiver IC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[14]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[15]  Hyung-Kyu Lim,et al.  A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL , 1997 .

[16]  Rahul Magoon,et al.  A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digital wireless communication , 1999 .

[17]  K. Kurokawa,et al.  Injection locking of microwave solid-state oscillators , 1973 .