Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach

On-chip inductive effects are becoming predominant in deepsubmicron (DSM) interconnects due to increasing clock speeds, circuit complexity and decreasing interconnect lengths. Inductance causes noise in the signal waveforms, which can adversely affect the performance of the circuit and signal integrity. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. This paper proposes a difference model approach to derive crosstalk in the transform domain. A closed form solution for crosstalk is obtained by incorporating initial conditions using difference model approach for distributed RLC interconnects. Simulation results show that the effect of inductive coupling forlong interconnects is significant but is almost negligible for local interconnects. It is also shown that when inductance is neglected, the proposed model reduces to a lumped RC model. Also, the analytical model response agrees very well that obtained with SPICE. All the experiments have been carried out for 90nm technology node using Cadence.s Dynamic Circuit Simulator SPECTRE©.

[1]  D. F. Wong,et al.  Closed form solutions to simultaneous buffer insertion/sizing and wire sizing , 2001, ACM Trans. Design Autom. Electr. Syst..

[2]  Jose E. Schutt-Aine,et al.  Optimal transient simulation of transmission lines , 1996 .

[3]  D. F. Wong,et al.  Shaping a VLSI wire to minimize delay using transmission line model , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[4]  Wayne Wei-Ming Dai,et al.  Optimal design of self-damped lossy transmission lines for multichip modules , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[5]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[6]  A. Richard Newton,et al.  Algorithms for the transient simulation of lossy interconnect , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Andrew B. Kahng,et al.  Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model , 1994, 31st Design Automation Conference.

[8]  Yao-Wen Chang,et al.  Timing modeling and optimization under the transmission line model , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[10]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[11]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[12]  Larry Pileggi,et al.  Modeling lossy transmission lines using the method of characteristics , 1996 .

[13]  R. J. Antinone,et al.  The modeling of resistive interconnects for integrated circuits , 1983 .

[14]  Martin D. F. Wong,et al.  Closed form solution to simultaneous buffer insertion/sizing and wire sizing , 1997, ISPD '97.

[15]  Denis Deschacht,et al.  Theoretical limits for signal reflections due to inductance for on-chip interconnections , 2000, SLIP '00.

[16]  Charlie Chung-Ping Chen,et al.  Optimal wire-sizing formula under the Elmore delay model , 1996, DAC '96.