A novel Josephson adder without carry propagation delay
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[1] Mititada Morisue,et al. A superconducting ternary systolic array processor , 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.
[2] Hiroshi Nakagawa,et al. A multichip superconducting microcomputer ETL-JC1 , 1991 .
[3] Hiroto Yasuura,et al. High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.
[4] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[5] A. Avizeinis,et al. Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .
[6] M. Morisue,et al. JCTL: a Josephson complementary ternary logic circuit , 1988, [1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic.