PGEN: A Novel Approach to Sequential Circuit Test Generation

A novel approach, called PGEN, is proposed to generate test patterns for resettable or nonresettable synchronous sequential circuits. PGEN contains two major routines, Sequential PODEM (S-PODEM) and a differential fault simulator. Given a fault, S-PODEM uses the concept of multiple time compression supported by a pulsating model, and generates a test vector in a single (yet compressed) time frame. Logic simulation (included in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logic simulation are well coordinated and significantly facilitate sequential circuit test generation. A modified version of differential fault simulation is also implemented and included in PGEN to cover other faults detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory.

[1]  Kewal K. Saluja,et al.  Fast test generation for sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[2]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[3]  Wu-Tung Cheng,et al.  Differential fault simulation for sequential circuits , 1990, J. Electron. Test..

[4]  L. H. Goldstein,et al.  Controllability/observability analysis of digital circuits , 1978 .

[5]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[6]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[7]  Vishwani D. Agrawal,et al.  Concurrent test generation and design for testability , 1989, IEEE International Symposium on Circuits and Systems,.

[8]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  J. Paul Roth,et al.  A Heuristic Algorithm for the Testing of Asynchronous Circuits , 1971, IEEE Transactions on Computers.

[10]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[11]  Irith Pomeranz,et al.  On achieving a complete fault coverage for sequential machines using the transition fault model , 1991, 28th ACM/IEEE Design Automation Conference.

[12]  S. Davidson,et al.  Sequential Circuit Test Generator (STG) benchmark results , 1989, IEEE International Symposium on Circuits and Systems,.

[13]  Parker,et al.  Design for Testability—A Survey , 1982, IEEE Transactions on Computers.

[14]  Michael J. Bending,et al.  Hitest: A Knowledge-Based Test Generation System , 1984, IEEE Design & Test of Computers.

[15]  Shianling Wu,et al.  A Sequential Circuit Test Generation System , 1985, ITC.

[16]  Peter Muth,et al.  A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.

[17]  Srinivas Devadas,et al.  Test generation and verification for highly sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Kwang-Ting Cheng,et al.  Functional test generation for finite state machines , 1990, Proceedings. International Test Conference 1990.