A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay

[1]  Luca Benini,et al.  Compilers and Operating Systems for Low Power , 2012, Springer US.

[2]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[3]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[4]  Sanjay Pant,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.

[5]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.

[6]  Tong Liu,et al.  Performance improvement with circuit-level speculation , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.

[7]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[8]  Vivek De,et al.  Sub-90nm technologies: challenges and opportunities for CAD , 2002, ICCAD 2002.

[9]  Naresh R. Shanbhag,et al.  Reliable and efficient system-on-chip design , 2004, Computer.

[10]  Tong Liu,et al.  Performance improvement with circuit-level speculation , 2000, MICRO 33.

[11]  Shih-Lien Lu.  Speeding Up Processing with Approximation Circuits , 2004, Computer.

[12]  Vivek De,et al.  Intrinsic MOSFET parameter fluctuations due to random dopant placement , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Augustus K. Uht.  Going beyond worst-case specs with TEAtime , 2004, Computer.

[14]  Toshinori Sato.  Constructive timing violation for improving energy efficiency , 2001 .