Side-Channel Attack Resilient Design of a 10T SRAM Cell in 7nm FinFET Technology

The non-invasive Side-Channel Attacks (SCA) for integrated circuits have been a concern for many years and Leakage Power Analysis (LPA) is among the leading threats for the IC security. For SRAM blocks, LPA would exploit the correlation between data in memory cell and its corresponding leakage power, and possibly decrypt the secret key inside the memory of crypto-systems. This paper proposes a new SRAM design countering against LPA, based on a recent low-power single-ended 9T cell design. Leakage balance issue for the 9T cell is discussed and a new cell design is presented. Simulation results confirm that the proposed SRAM cell preserves the advantages from the 9T design and have a well-balanced leakage behavior preventing against SCA.

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