A Time-Interleaved 14-bit 500MS/s Charge-Domain ADC with Mix-signal Mismatch Calibration
暂无分享,去创建一个
A two channel time-interleaved 14-bit 500MS/s charge domain pipelined ADC with mix-signal for-ground mismatch calibration method based on binary search is proposed. The offset and gain error mismatch between the two channels are calibrated in the mix-signal for-ground calibration. The 14-bit 500MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18$\mu$m CMOS process. Test results show the 14-bit 500MS/s ADC achieves the signal-to-noise ratio of 69.8 dBFS and the spurious free dynamic range of 82.3dB, with 72.1MHz input at 500MS/s, while consumes the power consumption of 365mW.
[1] Andrew Morgan,et al. A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration , 2010, IEEE Journal of Solid-State Circuits.
[2] L. Kushner,et al. A process-scalable low-power charge-domain 13-bit pipeline ADC , 2008, 2008 IEEE Symposium on VLSI Circuits.
[3] Janet Brunsilius,et al. A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration , 2014, IEEE Journal of Solid-State Circuits.