论文信息 - Design of D-Flip Flop using MTCMOS Technique

Design of D-Flip Flop using MTCMOS Technique

CMOS provide low power dissipation, comparatively high speed , high noise margin. D-flip flop is designed using mtcmos technique in which one transistor being clocked by short pulse train which is true single phase clocking (tspc) flip flop . In this paper D-flip flop implemented with mtcmos method is built using tanner eda software and the output is verified. In tanner, schematic diagram is designed in s-edit, truth table is observed on t-edit, the required waveforms are shown in w-edit, layout is specified in L-edit.

M. Sowmya | A. Divya | D. Sudharsan | Thenmozhi Ramyah

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