Capacitance coupled bus with negative delay circuit for high speed and low power (10 GB/s<500 mW) synchronous DRAMs

Capacitance coupled Bus (CcBus) with Negative Delay Circuit (NDC) architecture for high speed and low power Synchronous DRAMs (SDRAMs) has been developed. Data path power consumption is reduced to 1/5 (25mW@200MB/s). Transfer delay time is reduced to 1/2 (0.8 ns). High band width (10 GB/s) and low power (<500 mW) can be achieved. This 500 mW power consumption/package is an empirical value maintaining pause time in useful range. This architecture can keep Fill Frequencies (FF) in valuable region in Gbit-SDRAMs.