Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

[1]  Amer Baghdadi,et al.  FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding , 2020, 2020 International Workshop on Rapid System Prototyping (RSP).

[2]  Vladimir L. Petrovic,et al.  Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Shrinivas Kudekar,et al.  Design of Low-Density Parity Check Codes for 5G New Radio , 2018, IEEE Communications Magazine.

[4]  Brendan J. Frey,et al.  Factor graphs and the sum-product algorithm , 2001, IEEE Trans. Inf. Theory.

[5]  Xiqi Gao,et al.  Cellular architecture and key technologies for 5G wireless communication networks , 2014, IEEE Communications Magazine.

[6]  Emmanuel Boutillon,et al.  Extended Barrel-Shifter for Versatile QC-LDPC Decoders , 2020, IEEE Wireless Communications Letters.

[7]  Rüdiger L. Urbanke,et al.  Design of capacity-approaching irregular low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.

[8]  Hassan Harb,et al.  Fully Parallel Circular-Shift Rotation Network for Communication Standards , 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Shu Lin,et al.  QSN—A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Anuj Verma,et al.  A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio , 2020, 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID).

[11]  P. Glenn Gulak,et al.  A Multi-Gb/s Frame-Interleaved LDPC Decoder With Path-Unrolled Message Passing in 28-nm CMOS , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Joseph R. Cavallaro,et al.  Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[13]  Hideki Imai,et al.  Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..

[14]  Chung-An Shen,et al.  Low-Complexity LDPC Decoder for 5G URLLC , 2018, 2018 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

[15]  Anuj Verma,et al.  A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard , 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

[16]  Kyeongcheol Yang,et al.  Quasi-cyclic LDPC codes for fast encoding , 2005, IEEE Transactions on Information Theory.

[17]  Gerald E. Sobelman,et al.  A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.