Design of a CMOS limiting amplifier for the optical receiver

A limiting amplifier for the STM-4(622 Mbit/s) optical receiver in the SDH system is realized by native CMOS technology.The direct coupling technique is used to increase the voltage gain and reduce power dissipation,the multilevel coupling technique is used to increase the voltage gain,and active inductors are employed as loads to expand the bandwidth and get the stable DC operation point.Simulation of the circuit is carried out by adopting the software Smart Spice and CSMC-HJ 0.6 μm standard CMOS technologic parameters.Simulation results show that the amplifier exhibits an input dynamic range of 42 dB(from 4 mV to 500 mV) and an approximately constant double-end output voltage swing of 680 mV over a load of 50 Ω.