Influence of distance between adjacent tubes on SWCNT bundle interconnect delay and power dissipation

Influence of separation between adjacent tubes of various lengths and tube diameters, on delay and power dissipation in single walled carbon nanotube (SWCNT) bundle interconnect has been analyzed. The results are compared with those of currently used copper interconnects at 22nm technology node. SPICE simulation results reveal that delay increases with an increase in the separation between adjacent tubes for the entire range of length values and tube diameters whereas the reverse is true for power dissipation.

[1]  Shyh-Chyi Wong,et al.  Modeling of interconnect capacitance, delay, and crosstalk in VLSI , 2000 .

[2]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) , 2005, IEEE Electron Device Letters.

[3]  P. Ajayan,et al.  Reliability and current carrying capacity of carbon nanotubes , 2001 .

[4]  M. Meyyappan,et al.  Bottom-up approach for carbon nanotube interconnects , 2003 .

[5]  Mayank Kumar Rai,et al.  Influence of tube diameter on carbon nanotube interconnect delay and power output , 2011 .

[6]  Kaustav Banerjee,et al.  Performance analysis of carbon nanotube interconnects for VLSI applications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[7]  J. Hafner,et al.  Fabry - Perot interference in a nanotube electron waveguide , 2001, Nature.

[8]  B. Lengeler,et al.  Transport in ropes of carbon nanotubes: Contact barriers and luttinger liquid theory , 2004 .

[9]  W. Steinhögl,et al.  Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller , 2005 .

[10]  Arthur Nieuwoudt,et al.  Performance analysis of optimized carbon nanotube interconnect , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[11]  K. Banerjee,et al.  Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects , 2008, IEEE Transactions on Electron Devices.

[12]  Brajesh Kumar Kaushik,et al.  Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load , 2007, Integr..

[13]  J. Meindl,et al.  Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems , 2007, IEEE Transactions on Electron Devices.

[14]  A. Srivastava,et al.  Carbon nanotubes for next generation very large scale integration interconnects , 2010 .

[15]  Y. Massoud,et al.  On the Optimal Design, Performance, and Reliability of Future Carbon Nanotube-Based Interconnect Solutions , 2008, IEEE Transactions on Electron Devices.

[16]  D. Das,et al.  Analysis of Crosstalk in Single- and Multiwall Carbon Nanotube Interconnects and Its Impact on Gate Oxide Reliability , 2011, IEEE Transactions on Nanotechnology.

[17]  J. Meindl,et al.  Compact physical models for multiwall carbon-nanotube interconnects , 2006, IEEE Electron Device Letters.

[18]  P. Burke.  Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes , 2002 .

[19]  Arthur Nieuwoudt,et al.  Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits , 2006, JETC.

[20]  Franz Kreupl,et al.  Carbon nanotubes in interconnect applications , 2002 .

[21]  K. Banerjee,et al.  On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects , 2009, IEEE Transactions on Nanotechnology.