A new convolutional formulation of discrete cosine transform for systolic implementation
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[1] Pramod Kumar Meher. Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation , 2006, IEEE Transactions on Circuits and Systems for Video Technology.
[2] Thanos Stouraitis,et al. Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] H. T. Kung. Why systolic architectures? , 1982, Computer.
[4] Anil K. Jain. Fundamentals of Digital Image Processing , 2018, Control of Color Imaging Systems.
[5] Chein-Wei Jen,et al. A New Array Architecture for Prime-Length Discrete Cosine Transform , 1993, IEEE Trans. Signal Process..
[6] Keshab K. Parhi,et al. VLSI digital signal processing systems , 1999 .
[7] Keshab K. Parhi,et al. A novel systolic array structure for DCT , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.
[8] Doru Florin Chiper. Novel systolic array design for discrete cosine transform with high throughput rate , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[9] Pramod Kumar Meher. Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.