Physics-based compact modeling for nonclassical CMOS

Physics-based compact modeling, as opposed to the conventional empirical approach, is emphasized for nanoscale nonclassical CMOS. UFDG, a physics-based compact model for generic double-gate MOSFETs with ultra-thin bodies, is overviewed, and its applications to double- and (multiple) independent-gate FinFET device and circuit design are demonstrated.

[1]  E. Nowak,et al.  High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[2]  Jerry G. Fossum,et al.  Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology , 1995 .

[3]  G. O. Workman,et al.  A process/physics-based compact model for nonclassical CMOS device and circuit design , 2004 .

[4]  J. An,et al.  Physical insights on design and modeling of nanoscale FinFETs , 2003, IEEE International Electron Devices Meeting 2003.

[5]  J.G. Fossum,et al.  Multiple independent gate field effect transistor (MIGFET) - multi-fin RF mixer architecture, three independent gates (MIGFET-T) operation and temperature characteristics , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[6]  Chang Woo Oh,et al.  Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[7]  Bin Liu,et al.  Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits , 2001 .

[8]  V. Narayanan,et al.  Device design considerations for ultra-thin SOI MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[9]  Jerry G. Fossum.  A model too hot to handle , 2002 .

[10]  D. Fried,et al.  High-performance p-type independent-gate FinFETs , 2004, IEEE Electron Device Letters.

[11]  V. Trivedi,et al.  A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[12]  V. Trivedi,et al.  Scaling fully depleted SOI CMOS , 2003 .

[13]  V. Trivedi,et al.  Nanoscale FinFETs with gate-source/drain underlap , 2005, IEEE Transactions on Electron Devices.

[14]  D. Foty.  MOSFET modeling for circuit simulation , 1998 .

[15]  J. G. Fossum.  A model too hot to handle? [MOSFET model] , 2002 .

[16]  K. Natori.  Ballistic metal-oxide-semiconductor field effect transistor , 1994 .

[17]  L. Mathew,et al.  Physical insights regarding design and performance of independent-gate FinFETs , 2005, IEEE Transactions on Electron Devices.

[18]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[19]  J. G. Fossum,et al.  Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs , 2002 .

[20]  Hyung-Kyu Lim,et al.  Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's , 1983, IEEE Transactions on Electron Devices.

[21]  A. Vandooren,et al.  CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET) , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[22]  Keunwoo Kim,et al.  Double-gate CMOS: symmetrical- versus asymmetrical-gate devices , 2001 .

[23]  H.-S.P. Wong,et al.  Extreme scaling with ultra-thin Si channel MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[24]  M. Jurczak,et al.  Silicon-on-Nothing (SON)-an innovative process for advanced CMOS , 2000 .