A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
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N. Vallepalli | M. Bohr | U. Bhattacharya | F. Hamzaoglu | Kevin Zhang | Zhanping Chen | D. Murray | Yih Wang | Bo Zheng | D. Murray | M. Bohr | Kevin Zhang | F. Hamzaoglu | U. Bhattacharya | Zhanping Chen | N. Vallepalli | Yih Wang | B. Zheng
[1] N. Maeda,et al. A 300MHz 25/spl mu/A/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[2] N. Vallepalli,et al. SRAM design on 65nm CMOS technology with integrated leakage reduction scheme , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[3] Kouichi Kanda,et al. Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme , 2002, 15th Annual IEEE International ASIC/SOC Conference.
[4] S. Shimada,et al. A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor , 2004, IEEE Journal of Solid-State Circuits.
[5] K. Ishibashi,et al. 0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme , 2004, IEEE Journal of Solid-State Circuits.
[6] K. Itoh,et al. A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.
[7] P. Bai,et al. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..