Layer assignment for printed circuit boards and integrated circuits

The layer assignment problem arises in printed circuit board (PCB) and integrated circuit (IC) design. It involves the assignment of interconnect wiring to various planes of a PCB or to various layers of interconnect wires in an IC. This paper reviews basic techniques for layer assignment in both PCBs and ICs. Two types of layer assignment are considered: (1) constrained layer assignment in which routing of interconnections is given and the objective is to assign wires to specific layers, and (2) unconstrained, or topological, layer assignment, in which both the physical routing of interconnections and assignment of the wires to layers is sought. Various objective functions, such as via minimization and minimization of signal delays through interconnect lines are discussed. >

[1]  Chi-Ping Hsu.  Minimum-Via Topological Routing , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Yoji Kajitani,et al.  A graph- theoretic via minimization algorithm for two layer printed circuit boards , 1983 .

[3]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[4]  David Hung-Chang Du,et al.  Layer Assignment Problem for Three-Layer Routing , 1988, IEEE Trans. Computers.

[5]  Richard J. Enbody,et al.  Near-Optimal n-Layer Channel Routing , 1986, DAC 1986.

[6]  Donald S. Fussell,et al.  Topological channel routing [VLSI] , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Maciej J. Ciesielski,et al.  Layer assignment for VLSI interconnect delay minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  F. Hadlock,et al.  Finding a Maximum Cut of a Planar Graph in Polynomial Time , 1975, SIAM J. Comput..

[9]  Majid Sarrafzadeh,et al.  A new approach to topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Akihiro Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC.

[11]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[12]  R. Pinter.  Optimal layer assignment for interconnect , 1984 .

[13]  David Hung-Chang Du,et al.  Efficient Algorithms for Layer Assignment Problem , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Yun Kang Chen,et al.  Three-Layer Channel Routing , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Jack Edmonds,et al.  Maximum matching and a polyhedron with 0,1-vertices , 1965 .

[17]  Richard J. Enbody,et al.  Near-Optimal n-Layer Channel Routing , 1986, 23rd ACM/IEEE Design Automation Conference.

[18]  R. P. Dilworth,et al.  A DECOMPOSITION THEOREM FOR PARTIALLY ORDERED SETS , 1950 .

[19]  Malgorzata Marek-Sadowska.  An Unconstrained Topological Via Minimization Problem for Two-Layer Routing , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Jason Cong,et al.  On the k-layer planar subset and topological via minimization problems , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Maciej J. Ciesielski,et al.  An Optimum Layer Assignment for Routing in ICs and PCBs , 1981, 18th Design Automation Conference.