High-performance low-power carry select adder using dual transition skewed logic

In this paper, we present a low power and high performance Carry Select Adder (CSA) using Dual Transition Skewed Logic (DTSL) suitable for high noise immunity. We compared DTSL Carry Select Adder with domino and static CMOS adders with respect to performance, power consumption and area, using UMC 0.18µm technology. The comparison shows the superior properties of the DTSL over domino and the static CMOS logic: 19% to 27% improvement in power dissipation over domino with similar performance is observed.

[1]  Dinesh Somasekhar,et al.  Power and dynamic noise considerations in high-performance CMOS VLSI , 1999 .

[2]  Kaushik Roy,et al.  Skewed CMOS: Noise-immune high-performance low-power static circuit family , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[3]  Orest J. Bedrij.  Carry-Select Adder , 1962, IRE Trans. Electron. Comput..

[4]  Cheng-Kok Koh,et al.  Selectively clocked skewed logic (SCSL): a robust low-power logic style for high-performance applications , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[5]  C. M. Lee,et al.  High-speed compact circuits with CMOS , 1982 .