Substrate pump NMOS for ESD protection applications

The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.

[1]  C. Duvvury,et al.  ESD Protection Reliability in 1μM CMOS Technologies , 1986, 24th International Reliability Physics Symposium.

[2]  Kueing-Long Chen.  The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors , 1988 .

[3]  Amitava Chatterjee,et al.  Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[4]  C. Duvvury,et al.  Dynamic gate coupling of NMOS for efficient output ESD protection , 1992, 30th Annual Proceedings Reliability Physics 1992.

[5]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[6]  Charvaka Duvvury,et al.  Advanced CMOS protection device trigger mechanisms during CDM , 1995 .

[7]  Charvaka Duvvury,et al.  Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes , 1995, Proceedings of International Electron Devices Meeting.

[8]  S. Ramaswamy,et al.  Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations , 1996, Proceedings of International Reliability Physics Symposium.

[9]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1996 .

[10]  C. Duvvury,et al.  EOS/ESD analysis of high-density logic chips , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[11]  C. Duvvury,et al.  Design Methodology For Optimizing Gate Driven ESD Protection Circuits In Submicron Cmos Processes , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[12]  W.R. Anderson,et al.  Cross-referenced ESD protection for power supplies [microprocessors] , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[13]  J.C. Smith.  A substrate triggered lateral bipolar circuit for high voltage tolerant ESD protection applications , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[14]  C. Duvvury,et al.  Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes , 1998 .

[15]  A. Heringa,et al.  The effect of silicide on ESD performance , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).