An efficient methodology for noise characterization

In the recent years, the impact of nanometer process technologies has increased capacitive coupling and causing signal noise. Static noise analysis has become the most adopted method for performing signal integrity (SI) checks. This method requires noise characterization data in ASIC cell libraries to avoid spice simulations during chip level analysis. Characterization of noise parameters (output current voltage characteristics, noise rejection and noise propagation) accounts for around 60% of the total ASIC library characterization cycle time. This paper describes a novel and optimal method of measuring different noise parameters using data trend analysis, curve-fitting and interpolation techniques. It aims at reducing the characterization runtime without any loss in data accuracy and also without requiring extra inputs from the users. A runtime improvement of 4/spl times/ has been demonstrated using this methodology.