Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes

In this paper, we propose an ultrathin SiGe shell channel p-type FinFET for sub-10-nm technology nodes. Owing to the large valence band offset (VBO or <inline-formula> <tex-math notation="LaTeX">$\Delta {E}_{v}$ </tex-math></inline-formula>) between SiGe shell and Si fin, a hole quantum well is configured in the high-mobility SiGe region as the major conduction path. The proposed device is optimally designed and characterized in dc and ac. Here, high-<inline-formula> <tex-math notation="LaTeX">$\kappa$ </tex-math></inline-formula>/metal gate is adopted for strong gate controllability and the high degree of freedom in threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{{\text {th}}}$ </tex-math></inline-formula>) adjustment. For a high reliability, modeling of the mobility (<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>) and saturation velocity (<inline-formula> <tex-math notation="LaTeX">${v}_{{\text {sat}}}$ </tex-math></inline-formula>) is carried out for different Ge fractions (<inline-formula> <tex-math notation="LaTeX">${x}$ </tex-math></inline-formula>). The E<sub>g</sub> and VBO are also determined for different <inline-formula> <tex-math notation="LaTeX">${x}$ </tex-math></inline-formula> from empirical data. With the set of modeled values and various quantum-mechanical models, the proposed device has been simulated through rigorous 3-D technology computer-aided design simulation. The designed device shows a high scalability reaching down to L<sub>g</sub> = 5 nm. At L<sub>g</sub> of 5 nm with a driving voltage (V<sub>DD</sub>) of −0.5 V, a current gain cutoff frequency (f<sub>T</sub>) = 368.88 GHz, dynamic power = 0.055 fJ/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, and an intrinsic delay <inline-formula> <tex-math notation="LaTeX">$(\tau) = 0.37$ </tex-math></inline-formula> ps are achieved. This is confirmed by the potential low-power and high-speed operations with a strong gate controllability.

[1]  F. Trumbore,et al.  Solid solubilities of impurity elements in germanium and silicon , 1960 .

[2]  S. Laux,et al.  Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys , 1996 .

[3]  In Man Kang,et al.  RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs , 2011, IEEE Transactions on Electron Devices.

[4]  J. Hoyt,et al.  Super critical thickness SiGe-channel heterostructure p-type metal-oxide-semiconductor field-effect transistors using laser spike annealing , 2008 .

[5]  Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique , 2008 .

[6]  Jr John E. Smith Longitudinal Anisotropy of the High-Field Conductivity of n -Type Germanium at Room Temperature , 1969 .

[7]  P. Konkola,et al.  Implant dopant activation comparison between silicon and germanium , 2014, 2014 20th International Conference on Ion Implantation Technology (IIT).

[8]  P. Griffin,et al.  Critical thickness enhancement of epitaxial SiGe films grown on small structures , 2005 .

[9]  Hyoungsub Kim,et al.  Structural and Electrical Properties of EOT HfO2 (<1 nm) Grown on InAs by Atomic Layer Deposition and Its Thermal Stability. , 2016, ACS applied materials & interfaces.

[10]  A. R. Moore,et al.  Intrinsic Optical Absorption in Germanium-Silicon Alloys , 1958 .

[11]  E. J. Ryder,et al.  Mobility of Holes and Electrons in High Electric Fields , 1953 .

[12]  Judy L. Hoyt,et al.  Admittance spectroscopy measurements of band offsets in Si/Si1−xGex/Si heterostructures , 1992 .

[13]  O. Rozeau,et al.  Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[14]  N. Sugiyama,et al.  Kinetics of epitaxial growth of Si and SiGe films on (1 1 0) Si substrates , 2004 .

[15]  Wei D. Lu,et al.  Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor. , 2016, Nano letters.

[16]  G. Pei,et al.  FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .

[17]  Jerome Mitard,et al.  Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs , 2009 .

[18]  J. Hartmann,et al.  Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack , 2006, IEEE Transactions on Electron Devices.

[19]  K. Saraswat,et al.  Performance Evaluation of III-V Double-Gate n-MOSFETs , 2008, 2008 Device Research Conference.

[20]  B. Kaczer,et al.  SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI , 2013, IEEE Transactions on Electron Devices.

[21]  T. Liu,et al.  Segmented-channel Si1−xGex/Si pMOSFET for improved ION and reduced variability , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[22]  Martin,et al.  Theoretical calculations of heterojunction discontinuities in the Si/Ge system. , 1986, Physical review. B, Condensed matter.

[23]  Seongjae Cho,et al.  Design and analysis of nanowire p-type MOSFET coaxially having silicon core and germanium peripheral channel , 2016 .

[24]  T. Ghani,et al.  Front end stress modeling for advanced logic technologies , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[25]  J. Hartmann,et al.  Critical thickness for plastic relaxation of SiGe on Si(001) revisited , 2011 .

[26]  J. Sudijono,et al.  Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices , 2006, 2006 International Electron Devices Meeting.

[27]  A. Asenov Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[28]  A. Papon,et al.  Growth and structural properties of SiGe virtual substrates on Si(1 0 0), (1 1 0) and (1 1 1) , 2009 .

[29]  K. Oda,et al.  SiGe HBT Technology Based on a 0.13- $\mu{\rm m}$ Process Featuring an ${f}_{\rm MAX}$ of 325 GHz , 2014, IEEE Journal of the Electron Devices Society.

[30]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[31]  Injo Ok,et al.  High Transport Si/SiGe Heterostructures for CMOS Transistors with Orientation and Strain Enhanced Mobility , 2010, IEICE Trans. Electron..

[32]  Shinichi Takagi,et al.  Characterization of inversion-layer capacitance of holes in Si MOSFET's , 1999 .

[33]  L. Witters,et al.  Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[34]  J. Hartmann,et al.  Growth kinetics of Si and SiGe on Si(1 0 0), Si(1 1 0) and Si(1 1 1) surfaces , 2006 .

[35]  D. C. Houghton,et al.  Strain relaxation kinetics in Si(1-x)Ge(x)/Si heterostructures , 1991 .

[36]  Chun-Yen Chang,et al.  Analysis of high‐field hole transport characteristics in Si1−xGex alloys with a bond orbital band structure , 1996 .

[37]  A. Hikavyy,et al.  Growth of high Ge content SiGe on (110) oriented Si wafers , 2012 .

[38]  C. Canali,et al.  Hole drift velocity in silicon , 1975 .

[39]  Jongwook Jeon,et al.  A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[40]  J.L. Hoyt,et al.  Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs , 2008, IEEE Transactions on Electron Devices.

[41]  Junsoo Lee,et al.  Design of Poly-Si Junctionless Fin-Channel FET With Quantum-Mechanical Drift-Diffusion Models for Sub-10-nm Technology Nodes , 2016, IEEE Transactions on Electron Devices.

[42]  Shinichi Takagi,et al.  Evaluation of the valence band discontinuity of Si/Si/sub 1-x/Ge/sub x//Si heterostructures by application of admittance spectroscopy to MOS capacitors , 1998 .

[43]  P. Eyben,et al.  1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[44]  R. Apetz,et al.  Si1-xGex/Si valence band offset determination using current voltage characteristics , 1997 .

[45]  Y. Nishi,et al.  High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments , 2006, IEEE Transactions on Electron Devices.

[46]  Udayan Ganguly,et al.  Band gap bowing and band offsets in relaxed and strained Si1−xGex alloys by employing a new nonlinear interpolation scheme , 2013 .

[47]  Mobility enhancement in surface channel SiGe PMOSFETs with HfO2 gate dielectrics , 2003, IEEE Electron Device Letters.

[48]  Shinichi Takagi,et al.  Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction , 2001 .

[49]  M. Iwai,et al.  Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique , 2009, IEEE Transactions on Electron Devices.

[50]  K. Yahashi,et al.  High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique , 2006, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[51]  C. Canali,et al.  Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature , 1975, IEEE Transactions on Electron Devices.

[52]  Veena Misra,et al.  Analysis of boron strain compensation in silicon-germanium alloys by Raman spectroscopy , 2006 .

[53]  M. J. Kumar,et al.  Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review , 2004, IEEE Transactions on Device and Materials Reliability.

[54]  Cheewee Liu,et al.  The characteristic of HfO2 on strained SiGe , 2005 .

[55]  Kevin K. H. Chan,et al.  High Mobility High-Ge-Content SiGe PMOSFETs Using Al2O3/HfO2 Stacks With In-Situ O3 Treatment , 2017, IEEE Electron Device Letters.

[56]  M. Denais,et al.  NBTI degradation: From physical mechanisms to modelling , 2006, Microelectron. Reliab..

[57]  Krishna C. Saraswat,et al.  Ge based high performance nanoscale MOSFETs , 2005 .

[58]  Shinichi Takagi,et al.  Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique , 2003 .

[59]  Victor Ryzhii,et al.  High-Field Electron Transport in SiGe Alloy , 1994 .

[60]  In Man Kang,et al.  Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation , 2011 .