Scalable Digital CMOS Comparator using a Parallel Prefix Tree

: Comparators are the key design elements for a wide range of applications like scientific computation (graphics and image/signal processing),test circuit applications (jitter measurements, signature analyzers, and built-in self test circuits) and for general-purpose processor components (associative memories, load-store queue buffers, translation look-aside buffers, branch target buffers) and many other CPU argument comparison blocks .In this project a 16,32,64 bit comparator architectures is designed by using parallel prefix structure . This project evaluates the successful results as per requirement and specifications. In existing system ,the parallel prefix structure is designed for 16 ,32 and 64 bit architectures and the reports from the Xilinx tool concludes that for every bit range doubles the delay , memory , LUT and power has not doubled up to the mark. But In the proposed design of my project, each and every element in the parallel prefix structure will be replaced by universal logic (multiplexer) and the obtained results will be compared with existed design for the same device specifications. By performing this modification in the architecture will leads to reduction in power consumption and in delay parameters.