Probabilistic CMOS ( PCMOS ) Logic for Nanoscale Circuit Design
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Zhi-Hui Kong | Krishna V. Palem | Pinar Korkmaz | K. Yeo | K. Palem | Pinar Korkmaz | Kiat-Seng Yeo | Z. Kong
[1] Krishna V. Palem,et al. Probabilistic system-on-a-chip architectures , 2007, TODE.
[2] Krishna V. Palem,et al. Probabilistic arithmetic and energy efficient embedded signal processing , 2006, CASES '06.
[3] Pinar Korkmaz,et al. Advocating Noise as an Agent for Ultra-Low Energy Computing: Probabilistic Complementary Metal-Oxide-Semiconductor Devices and Their Characteristics , 2006 .
[4] Shekhar Y. Borkar,et al. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.
[5] R.I. Bahar,et al. A probabilistic-based design methodology for nanoscale computation , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).
[6] L. Kish. End of Moore's law: thermal (noise) death of integration in micro and nano electronics , 2002 .
[7] J. Meindl,et al. Limits on silicon nanoelectronics for terascale integration. , 2001, Science.
[8] A. Sinha,et al. JouleTrack-a Web based tool for software energy profiling , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).