A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-/spl mu/m CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems.

[1]  H.-L. Lou,et al.  Implementing the Viterbi algorithm , 1995, IEEE Signal Process. Mag..

[2]  Keshab K. Parhi.  High-speed VLSI architectures for Huffman and Viterbi decoders , 1992 .

[3]  R. E. Peile,et al.  Stanford Telecom VLSI design of a convolutional decoder , 1989, IEEE Military Communications Conference, 'Bridging the Gap. Interoperability, Survivability, Security'.

[4]  Paul H. Siegel,et al.  VLSI architectures for metric normalization in the Viterbi algorithm , 1990, IEEE International Conference on Communications, Including Supercomm Technical Sessions.

[5]  K. Azadet,et al.  A low power 128-tap digital adaptive equalizer for broadband modems , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[6]  C. Rader.  Memory Management in a Viterbi Decoder , 1981, IEEE Trans. Commun..

[7]  Teresa H. Meng,et al.  A 140-Mb/s, 32-state, radix-4 Viterbi decoder , 1992 .

[8]  C. Shung,et al.  Generalized trace back techniques for survivor memory management in the Viterbi algorithm , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[9]  Heinrich Meyr,et al.  Trellis pipeline-interleaving: a novel method for efficient Viterbi decoder implementation , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[10]  Jens Sparsø,et al.  An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures , 1991 .

[11]  A. N. Willson,et al.  Low-power Viterbi decoder for CDMA mobile terminals , 1998 .

[12]  Mary Jane Irwin,et al.  Area-time-power tradeoffs in parallel adders , 1996 .

[13]  J. Hindering,et al.  CDMA Mobile Station Modem ASIC , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[14]  P. Glenn Gulak,et al.  Architectural tradeoffs for survivor sequence memory management in Viterbi decoders , 1993, IEEE Trans. Commun..

[15]  Gerhard Fettweis,et al.  Feedforward architectures for parallel viterbi decoding , 1991, J. VLSI Signal Process..

[16]  Jan M. Rabaey,et al.  A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[17]  David G. Messerschmitt,et al.  Algorithms and architectures for concurrent Viterbi decoding , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[18]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[19]  Hui-Ling Lou.  Implementing the Viterbi Algorithm Fundamentals and real-time issues for processor designers , 1995 .

[20]  Keshab K. Parhi,et al.  Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).