Fully Dynamic Switch-Level Simulation of CMOS Circuits

A new algorithm for switch-level simulation is suggested which allows the simulator to be fully dynamic, i.e., several signals may propagate in the network simultaneously. It is shown how this algorithm can be combined with a timing model. Finally, it is demonstrated how a simulator based on this algorithm can handle problems such as charge sharing and clock skewing in general CMOS circuits.

[1]  Hugo De Man,et al.  Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  John K. Ousterhout.  A Switch-Level Timing Verifier for Digital MOS VLSI , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Christer Svensson,et al.  Switch-level simulation and the pass transistor EXOR gate , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  M.H. Heydemann.  A Survey of MOS Logic Simulation Tools , 1983, ESSCIRC '83: Ninth European Solid-State Circuits Conference.

[5]  Randal E. Bryant,et al.  A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.

[6]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..