Minimizing the runtime partial reconfiguration overheads in reconfigurable systems

Configuration overhead is a major performance bottleneck of the partial reconfiguration process. In this paper, we propose a combination of two techniques to minimize the partial reconfiguration performance overhead. First, we design and implement fully streaming DMA engines to achieve a near perfect configuration throughput. Second, we exploit the configuration data redundancy through Run-Length Encoding to compress the configuration bitstreams, and we implement an intelligent ICAP (Internal Configuration Access Port) controller to perform decompression at runtime. The results show that our design achieve an effective configuration data transfer throughput that well surpasses the upper bound of data transfer throughput, 400 Mbytes/s. Specifically, our fully stream DMA engines reduce the configuration time from the range of seconds to the range of milliseconds, a more than 1000-fold improvement. In addition, our simple compression scheme achieves significant reduction of bitstream size and results in a decompression circuit with negligible hardware overhead.

[1]  Tulika Mitra,et al.  Configuration bitstream compression for dynamically reconfigurable FPGAs , 2004, ICCAD 2004.

[2]  Viktor K. Prasanna,et al.  Configuration compression for FPGA-based embedded systems , 2001, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Zhimin Gu,et al.  Hardware-assisted middleware: Acceleration of garbage collection operations , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

[4]  Axel Jantsch,et al.  Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[5]  Michael J. Wirthlin,et al.  FPGA partial reconfiguration via configuration scrubbing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[6]  Francky Catthoor,et al.  A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware [multimedia applications] , 2005, Design, Automation and Test in Europe.

[7]  Edwin V. Bonilla,et al.  Predicting best design trade-offs: A case study in processor customization , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Jih-Ching Chiu,et al.  The Multi-context Reconfigurable Processing Unit for Fine-grain Computing , 2008, J. Inf. Sci. Eng..

[9]  Zhiyuan Li,et al.  Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation , 2002, FPGA '02.

[10]  Jean-Luc Gaudiot,et al.  On energy efficiency of reconfigurable systems with run-time partial reconfiguration , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

[11]  Viktor K. Prasanna,et al.  Configuration compression for FPGA-based embedded systems , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Zhiyuan Li,et al.  Configuration Compression for Virtex FPGAs , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[13]  Tulika Mitra,et al.  Configuration bitstream compression for dynamically reconfigurable FPGAs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[14]  Jürgen Becker,et al.  Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[15]  Bin Zhang,et al.  A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[16]  Alessandro Forin,et al.  Relocation and Automatic Floor-planning of FPGA Partial Configuration Bit-Streams , 2008 .

[17]  LukWayne,et al.  Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware , 2008 .

[18]  Zhimin Gu,et al.  Achieving middleware execution efficiency: hardware-assisted garbage collection operations , 2010, The Journal of Supercomputing.

[19]  Wayne Luk,et al.  Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware , 2008, TRETS.

[20]  Axel Jantsch,et al.  Run-time Partial Reconfiguration speed investigation and architectural design space exploration , 2009, 2009 International Conference on Field Programmable Logic and Applications.