An evaluation of bipartitioning techniques

Logic partitioning is an important issue in VLSI CAD, and has been an area of active research for at least the last 25 years. Numerous approaches have been developed and many different techniques have been combined for a wide range of applications. In this paper, we examine many of the existing techniques for logic bipartitioning and present a methodology for determining the best mix of approaches The result is a novel bipartitioning algorithm that includes both new and preexisting techniques. Our algorithm produces results that are at least 16% better than the state of the art while also being efficient in run time.

[1]  Ernst G. Ulrich,et al.  Clustering and linear placement , 1972, DAC '72.

[2]  Balakrishnan Krishnamurthy,et al.  An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.

[3]  Andrew B. Kahng,et al.  New spectral methods for ratio cut partitioning and clustering , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Charles J. Alpert,et al.  Spectral Partitioning: The More Eigenvectors, The Better , 1995, 32nd Design Automation Conference.

[5]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[6]  Konrad Doll,et al.  Partitioning Very Large Circuits Using Analytical Placement Techniques , 1994, 31st Design Automation Conference.

[7]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[8]  Chingwei Yeh,et al.  Optimization by iterative improvement: an experimental evaluation on two-way partitioning , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Gaetano Borriello,et al.  Logic Partition Orderings for Multi-FPGA Systems , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[10]  ZVI GALIL,et al.  Efficient algorithms for finding maximum matching in graphs , 1986, CSUR.

[11]  A. J. Stone,et al.  Logic partitioning , 1966, DAC.

[12]  Frank Thomson Leighton,et al.  Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms , 1989, 26th ACM/IEEE Design Automation Conference.

[13]  Chingwei Yeh,et al.  A general purpose multiple way partitioning algorithm , 1991, DAC '91.

[14]  Hans Jürgen Prömel,et al.  Finding clusters in VLSI circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[15]  D. F. Wong,et al.  Efficient network flow based min-cut balanced partitioning , 1994, ICCAD 1994.

[16]  C. Yeh,et al.  A probabilistic multicommodity-flow solution to circuit clustering problems , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[17]  Carl Sechen,et al.  A timing driven N-way chip and multi-chip partitioner , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[18]  Dennis J.-H. Huang,et al.  On implementation choices for iterative improvement partitioning algorithms , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[19]  Jason Cong,et al.  A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design , 1993, 30th ACM/IEEE Design Automation Conference.

[20]  Ulrich Weinmann.  FPGA partitioning under timing constraints , 1994 .

[21]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..