A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

The demand for massive MIMO, digital beamforming, and increased bandwidth communication dramatically increases the complexity of the remote radio head in future cellular base-stations. This complexity issue can be addressed by RF transceiver SoCs incorporating multiple direct RF radio transceivers, which have clear advantages over conventional architectures and are enabled by high-performance digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). However, the sampling clock for these high-performance data converters must fulfill very stringent in-band and out-of-band spectral mask requirements, which are hard to meet with RF frequency synthesizers integrated on the SoC. All digital PLLs (ADPLLs) utilize the advantages of scaled nodes and rely on advanced digital signal-processing techniques to boost performance. Sub-sampling ADPLLs (SS-ADPLL) enable the usage of an energy-efficient time-to-digital converter (TDC) since the TDC noise is multiplied by a smaller factor [1]. This work presents a sub-sampling ADPLL with stochastic-flash TDC (SFTDC) and coupled dual-core DCO achieving 47.3fsrms jitter performance in 16nm FinFET CMOS.

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