Digital Implementation of Hierarchical

A formal methodology drives the design and re- alization of a digital very large-scale integration (VLSI) device supporting hierarchical vector quantization (HVQ) in compu- tation-intensive coding applications. The hardware-oriented model-selection approach enhances the Minimum Description Length criterion with circuit-related aspects that allow consistent and efficient design. The resulting model parameters drive the subsequent realization in digital circuitry, which has first been implemented in field-programmable gate array (FPGA) tech- nology to verify its correctness. The eventual VLSI realization results in an HVQ chip providing cost-effective, computationally efficient real-time performances. Real-world applications support the consistency of the vector quantization approach and the effectiveness of the HVQ device. Index Terms—Digital very large-scale integration (VLSI), min- imum description length (MDL), vector quantization (VQ).

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