Normally-Off LPCVD-SiNx/GaN MIS-FET With Crystalline Oxidation Interlayer

Developing effective technique to protect the etched- GaN surface from the degradation in a high-temperature (i.e., at ~ 780°C) process, such as low-pressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining such a protection layer using oxygen-plasma treatment followed by <italic>in situ</italic> annealing prior to the LPCVD-SiN<sub>x</sub> deposition. A sharp and stable crystalline oxidation interlayer (COIL) between the LPCVD-SiN<sub>x</sub> and etched-GaN was successfully formed. The LPCVD-SiN<sub>x</sub>/GaN MIS-FETs with COIL deliver normally-off operation with a <inline-formula> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula> of 1.15 V, small on-resistance, small hysteresis, and thermally stable <inline-formula> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula>.

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