Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design
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[1] S. Winters,et al. A differential floating gate capacitance mismatch measurement technique , 2000, ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095).
[2] D. Sealer,et al. Precision Capacitor Ratio Measurement Technique for Integrated Circuit Capacitor Arrays , 1979, IEEE Transactions on Instrumentation and Measurement.
[3] Stephen H. Lewis,et al. A 10-b 20-Msample/s analog-to-digital converter , 1992 .
[4] Kwang Young Kim,et al. A 10-b, 100-MS/s CMOS A/D converter , 1997 .
[5] P. R. Gray,et al. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.