PHIL implementation of a MVDC fault management test bed for ship power systems based on megawatt-scale modular multilevel converters

Fault management in a shipboard, medium voltage dc (MVDC) integrated power system (IPS) is a ship-wide function requiring a rapid and highly-coordinated response of several different protection strategies. This paper describes the design and implementation of a MVDC fault management test bed at FSU-CAPS that is capable of demonstrating the relative performance of candidate MVDC protection techniques, both individually, and coordinated with other elements of the overall IPS protection system. The test bed described employs power-hardware-in-the-loop (PHIL) interfaces with a Real-time Digital Simulator (RTDS) model of a MVDC IPS. The hardware portion of the PHIL test setup consists of four, megawatt-scale, full-bridge, modular multi-level converters (MMCs) and a scaled version of a full-size MVDC ring bus for Naval surface combatants. This paper discusses the issues associated with implementing the lengthy cable runs of the scaled ring bus in FSU-CAPS' MVDC test building. It also explores application of the test bed to demonstrate the protection system response of several dc fault management methodologies.