Via configurable three-input lookup-tables for structured ASICs

In this article we study layout and circuit implementations of 3-input lookup table (3-LUT) for via configurable structured ASIC. We present a new 3-LUT circuit and several layout designs. We also propose a method to improve the delay of any logic function with fewer inputs. A 3-LUT, being able to realize all the 256 3-input functions, enables us to synthesize a circuit using both a standard cell synthesizer and an FPGA technology mapper such as FlowMap. Our study shows that circuits synthesized using a standard-cell synthesizer usually achieves better timing than that obtained by FlowMap. Our study further shows that the well-known 3-LUT implemented with multiplexers achieves better timing, area, and power dissipation. Our methodology can be also employed to study look-up tables with more inputs.

[1]  Andrzej J. Strojwas,et al.  Design methodology for IC manufacturability based on regular logic-bricks , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[2]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Malgorzata Marek-Sadowska,et al.  Via-configurable routing architectures and fast design mappability estimation for regular fabrics , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[4]  Deepak D. Sherlekar.  Design considerations for regular fabrics , 2004, ISPD '04.

[5]  Andrzej J. Strojwas,et al.  Exploring regular fabrics to optimize the performance-cost trade-off , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  Jamil Kawa,et al.  Design automation for mask programmable fabrics , 2004, Proceedings. 41st Design Automation Conference, 2004..

[7]  Sunil P. Khatri,et al.  A metal and via maskset programmable VLSI design methodology using PLAs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[8]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[9]  N. Maeda,et al.  Design methodology and tools for NEC electronics' structured ASIC ISSP , 2004, ISPD '04.

[10]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[11]  Mosong Cheng,et al.  A lithography-friendly structured ASIC design approach , 2008, GLSVLSI '08.

[12]  Robert K. Brayton,et al.  PLA-based regular structures and their synthesis , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Lawrence T. Pileggi,et al.  Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics , 2003, FPL.

[14]  Lawrence T. Pileggi,et al.  Exploring logic block granularity for regular fabrics , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  Lawrence T. Pileggi,et al.  An architectural exploration of via patterned gate arrays , 2003, ISPD '03.

[16]  Yu-Wen Tsai,et al.  Structured ASIC, evolution or revolution? , 2004, ISPD '04.

[17]  Malgorzata Marek-Sadowska,et al.  Designing via-configurable logic blocks for regular fabric , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Sunil P. Khatri,et al.  A Structured ASIC Design Approach Using Pass Transistor Logic , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[19]  Takeshi Fujino,et al.  Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing , 2008, IEICE Trans. Electron..

[20]  Behrooz Zahiri.  Structured ASICs: opportunities and challenges , 2003, Proceedings 21st International Conference on Computer Design.

[21]  Antonio Rubio,et al.  Via-configurable transistors array: a regular design technique to improve ICs yield , 2007 .

[22]  Rung-Bin Lin,et al.  Standard Cell Like Via-Configurable Logic Block for Structured ASICs , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.