Test resource partitioning and reduced pin-count testing based on test data compression

We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and on-chip decompression. It makes effective use of frequency-directed run-length codes, internal scan chains, and boundary scan chains. The compression/decompression scheme decreases test data volume and the amount of data that has to be transported from the tester to the SOC We show via analysis as well as through experiments that the proposed TRP scheme reduces testing time and allows the use of a slower tester with fewer I/O channels. Finally, we show that an uncompacted test set applied to an embedded core after on-chip decompression is likely to increase defect coverage.

[1]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[2]  Harald P. E. Vranken,et al.  Enhanced Reduced Pin-Count Test for Full-Scan Design , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[3]  Irith Pomeranz,et al.  On the effects of test compaction on defect coverage , 1996, Proceedings of 14th VLSI Test Symposium.

[4]  Krishnendu Chakrabarty,et al.  Test Resource Partitioning for SOCs , 2001, IEEE Des. Test Comput..

[5]  Nur A. Touba,et al.  Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Carlos Delgado Kloos,et al.  Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Krishnendu Chakrabarty,et al.  Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[8]  Marc R. Faucher,et al.  Low-Cost Testing of High-Density Logic Components , 1990, IEEE Des. Test Comput..

[9]  Krishnendu Chakrabarty,et al.  Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[10]  Yervant Zorian.  Testing the monster chip , 1999 .

[11]  David F. Heidel,et al.  High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[12]  Dong Sam Ha,et al.  AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT , 1991, 1991, Proceedings. International Test Conference.

[13]  Krishnendu Chakrabarty,et al.  System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Janak H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[15]  John G. Petrovick,et al.  Low-cost testing of high-density logic components , 1989, IEEE Design & Test of Computers.

[16]  Irith Pomeranz,et al.  Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).