Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability

This paper presents a design-for-testability method that transforms a given SoC into consecutively testable one under power constraint. When a power constraint and a user defined importance ratio between area overhead and test time are given, the proposed method can create an optimal TAM design and a test schedule for the importance ratio under the power constraint with low computational cost. Experimental results show that the proposed method can achieve area and time co-optimization under power constraint. Moreover, the proposed method can obtain better results for SoCs without power constraint compared to test bus method and our previous method based on consecutive testability of SoCs

[1]  Kewal K. Saluja,et al.  Test Scheduling and Control for VLSI Built-In Self-Test , 1988, IEEE Trans. Computers.

[2]  Christos A. Papachristou,et al.  Structural Fault Testing of Embedded Cores Using Pipelining , 1999, J. Electron. Test..

[3]  Hideo Fujiwara,et al.  Design for consecutive transparency of cores in system-on-a-chip , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[4]  Zebo Peng,et al.  A reconfigurable power-conscious core wrapper and its application to soc test scheduling , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[5]  Hideo Fujiwara,et al.  Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores , 2002, J. Electron. Test..

[6]  Yervant Zorian,et al.  Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2002, J. Electron. Test..

[8]  Erik Jan Marinissen,et al.  A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Hideo Fujiwara,et al.  Area and time co-optimization for system-on-a-chip based on consecutive testability , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[10]  Yervant Zorian,et al.  Testing Embedded-Core-Based System Chips , 1999, Computer.

[11]  Erik Jan Marinissen,et al.  The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs , 2002, J. Electron. Test..

[12]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[13]  Srivaths Ravi,et al.  Testing of core-based systems-on-a-chip , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Prab Varma,et al.  A unifying methodology for intellectual property and custom logic testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[15]  Yervant Zorian,et al.  On IEEE P1500's Standard for Embedded Core Test , 2002, J. Electron. Test..