Failure mechanism for input buffer under CDM test

The influence of the body layout on the charged device model (CDM) failure site and the robustness of the input buffer is explored. The failure analysis results confirm that the gate oxide is damaged. The failure site can be moved from the region above the channel to the overlap region between the source and the gate once the body layout is cut from a ring into a small segment, providing direct evidence demonstrating that the CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the V ss bus line. Otherwise, changing the body layout of the input buffer transistor does not vary the failure location.

[1]  J. R. Shih,et al.  The failure mechanism re-investigation Of ESD device on EPI wafer , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[2]  Wolfgang Stadler,et al.  CDM tests on interface test chips for the verification of ESD protection concepts , 2007 .

[3]  Jian-Hsing Lee,et al.  The study of sensitive circuit and layout for CDM improvement , 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

[4]  Bonnie E. Weir,et al.  Gate dielectric breakdown in the time-scale of ESD events , 2005, Microelectron. Reliab..