Process-induced skew variation for scaled 2-D and 3-D ICs

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented at scaled technology nodes and for a 3-D circuit with an increasing number of planes is investigated in this paper. An accurate model used to describe the effect of the proper sources of variations on each of these design approaches is proposed. The distribution of the pair-wise skew variation is obtained for single scaled or multi-plane (not scaled) clock distribution networks. The accuracy of the presented statistical skew model is verified through Monte-Carlo simulations. As shown in this paper, the clock skew variation due to technology scaling and/or die stacking exhibits a considerably different behavior. A comparison between these two design paradigms is offered such that the appropriate technology node and number of planes are selected to produce a low clock skew variation and high operating frequency. A popular global clock tree topology is employed in a planar (2-D) circuit where technology scaling is applied and in a 3-D circuit with an increasing number of planes. For this clock tree topology, the maximum supported clock frequency increases from 2.75 GHz to 3.74 GHz by proper die-stacking at a 90 nm technology node. 3-D integration is shown to be an alternative to reduce skew variation without the need of aggressive technology scaling.

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