Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 μW) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 μW and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79-μW (53.36-μW) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

[1]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[2]  Keivan Navi,et al.  Two new low-power Full Adders based on majority-not gates , 2009, Microelectron. J..

[3]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Chip-Hong Chang,et al.  A novel hybrid pass logic with static CMOS output drive full-adder cell , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[5]  Ehsan Kargaran,et al.  Design of new full adder cell using hybrid-CMOS logic style , 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

[6]  P. Prashanth,et al.  Architecture of adders based on speed, area and power dissipation , 2011, 2011 World Congress on Information and Communication Technologies.

[7]  Mark Vesterbacka.  A 14-transistor CMOS full adder with full voltage-swing nodes , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[8]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[9]  Mohamed A. Elgamel,et al.  Novel design methodology for high-performance XOR-XNOR circuit design , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[10]  Chip-Hong Chang,et al.  A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits , 2005 .

[11]  Vishant,et al.  Design analysis of XOR (4T) based low voltage CMOS full adder circuit , 2011, 2011 Nirma University International Conference on Engineering.

[12]  Ian O'Connor,et al.  ULPFA: A New Efficient Design of a Power-Aware Full Adder , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[14]  Mónico Linares Aranda,et al.  CMOS Full-Adders for Energy-Efficient Arithmetic Applications , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[16]  Xunwei Wu,et al.  Design of ternary CMOS circuits based on transmission function theory , 1988 .

[17]  Yingtao Jiang,et al.  Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates , 2002 .

[18]  D. Radhakrishnan,et al.  Low-voltage low-power CMOS full adder , 2001 .

[19]  Gaetano Palumbo,et al.  Mixed Full Adder topologies for high-performance low-power arithmetic circuits , 2007, Microelectron. J..

[20]  Yu-Cherng Hung,et al.  A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[21]  Mónico Linares Aranda,et al.  Hybrid adders for high-speed arithmetic circuits: A comparison , 2010, 2010 7th International Conference on Electrical Engineering Computing Science and Automatic Control.

[22]  Omid Kavehei,et al.  A novel low-power full-adder cell for low voltage , 2009, Integr..

[23]  Mostafa Rahimi Azghadi,et al.  A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter , 2009, Microelectron. J..

[24]  Magdy A. Bayoumi,et al.  Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.