PLL/DLL system noise analysis for low jitter clock synthesizer design

This paper presents an analytical model for timing jitter accumulation in ring-oscillator based phase-locked-loops (PLL). The timing jitter of the system is shown to depend on the jitter in the ring-oscillator and an accumulation factor which is inversely proportional to the bandwidth of the phase-locked-loop. Further analysis shows that for delay-locked-loops (DLL), which use an inverter delay chain that is not configured as a ring-oscillator, there is no noise enhancement since noise jitter events do not contribute to the starting point of the next clock cycle. Finally, theoretical predictions for overall jitter are compared to behavioral simulations with good agreement.<<ETX>>