Automatic Visual Architecture Generation System for Efficient HDL Debugging

In this paper we propose anew EC AD software for efficiently analyzing and debugging of digital architecture implemented in Verilog HDL or VHDL codes. This software firstly elaborates HDL codes so as to extract internal architecture structure, then generates several graphical aids such as hierarchical schematics by applying placement and routing algorithm, object tree to show configuration of each module, instance tree to show hierarchical structure of instances, and SPD (signal propagation diagram) to show internal interconnections. It is more important function that same objects in different views - HDL codes, object tree, instance tree, SPD, waveform - can be highlighted at the starting any object These functions are sure to improve efficiency of manual job to fix bugs or to analyze HDL codes.

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