Speeding up SAT-Based ATPG Using Dynamic Clause Activation

SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduced using a SAT-based ATPG approach. In contrast to structural ATPG, SAT solvers work on a Boolean formula in Conjunctive Normal Form (CNF). This results in some disadvantages for SAT solvers when applied to ATPG, e.g. CNF transformation time and loss of structural knowledge. As a result, SAT-based ATPG algorithms are very robust for hard-to-test faults, but suffer from the overhead for easy-to-test faults. We propose the SAT technique Dynamic Clause Activation (DCA) in order to reduce the run time gap between structural and SAT-based ATPG algorithms and, at the same time, retain the high level of robustness. Using DCA, the SAT solver works on a partial formula of a logic circuit which is dynamically extended during the search process using structural knowledge. Furthermore, efficient dynamic learning techniques can be easily integrated within the proposed technique. The approach is evaluated on large industrial circuits.

[1]  J. P. Marques,et al.  GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .

[2]  Rolf Drechsler,et al.  Test Pattern Generation using Boolean Proof Engines , 2009 .

[3]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[5]  Chih-Chun Lee,et al.  QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[6]  R. Drechsler,et al.  Improving Test Pattern Compactness in SAT-based ATPG , 2007, 16th Asian Test Symposium (ATS 2007).

[7]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[8]  P. Ashar,et al.  Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[9]  Sharad Malik,et al.  Considering circuit observability don't cares in CNF satisfiability , 2005, Design, Automation and Test in Europe.

[10]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Sharad Malik,et al.  Efficient conflict driven learning in a Boolean satisfiability solver , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[12]  Rolf Drechsler,et al.  Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques , 2009, 2009 14th IEEE European Test Symposium.

[13]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[14]  Kwang-Ting Cheng,et al.  TranGen: a SAT-based ATPG for path-oriented transition faults , 2004 .

[15]  Ofer Shtrichman.  Pruning Techniques for the SAT-Based Bounded Model Checking Problem , 2001 .

[16]  Rolf Drechsler,et al.  On Acceleration of SAT-Based ATPG for Industrial Designs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Joao Marques-Silva,et al.  Robust search algorithms for test pattern generation , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[18]  Rolf Drechsler,et al.  Improved SAT-based Reachability Analysis with Observability Don't Cares , 2008, J. Satisf. Boolean Model. Comput..

[19]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Kwang-Ting Cheng,et al.  A circuit SAT solver with signal correlation guided learning , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.