Optimal Matrix Multiplication on Fault-Tolerant VLSI Arrays

A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy testability and reconfigurability is described. All signals in the array travel only a constant distance (independent of array size) in any clock cycle. An optimal-time algorithm, designed for multiplying matrices, is described. The algorithm is an efficient simulation of a 2-D systolic algorithm for multiplying matrices. >

[1]  J. Greene,et al.  Area and Delay Penalties in Restructurable Wafer-Scale Arrays , 1983 .

[2]  H. T. Kung,et al.  Systolic Arrays for (VLSI). , 1978 .

[3]  Peter Joseph Varman.  Wafer-scale integration of linear processor arrays , 1983 .

[4]  Melvin A. Breuer,et al.  On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays , 1984, IEEE Transactions on Computers.

[5]  John E. Savage,et al.  Area-Time Tradeoffs for Matrix Multiplication and Related Problems in VLSI Models , 1981, J. Comput. Syst. Sci..

[6]  David W. L. Yen,et al.  Systolic Processing and an Implementation for Signal and Image Processing , 1982, IEEE Transactions on Computers.

[7]  Arnold L. Rosenberg,et al.  The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors , 1983, IEEE Transactions on Computers.

[8]  W. Morven Gentleman,et al.  Some Complexity Results for Matrix Computations on Parallel Processors , 1978, JACM.

[9]  I. V. Ramakrishnan,et al.  Modular Matrix Multiplication on a Linear Array , 1984, IEEE Trans. Computers.

[10]  Kye Sherrick Hedlund.  Wafer scale integration of configurable, highly parallel processors , 1982 .

[11]  Franco P. Preparata,et al.  Area-Time Optimal VLSI Networks for Multiplying Matrices , 1980, Inf. Process. Lett..

[12]  Bernard Chazelle,et al.  A Model of Computation for VLSI with Related Complexity Results , 1985, J. ACM.

[13]  I. V. Ramakrishnan,et al.  On Matrix Multiplication Using Array Processors , 1985, ICALP.

[14]  J. I. Raffel.  On the Use of Nonvolatile Programming Links for Restructurable VLSI , 1979 .

[15]  Frank Thomson Leighton,et al.  Wafer-Scale Integration of Systolic Arrays , 1985, IEEE Trans. Computers.

[16]  Thomas Ottmann,et al.  The Power of a One-Dimensional Vector of Processors , 1980, WG.

[17]  I. V. Ramakrishnan,et al.  A Fault-Tolerant VLSI Matrix Multiplier , 1986, ICPP.

[18]  I. V. Ramakrishnan,et al.  SYSTOLIC MATRIX MULTIPLICATION ON A LINEAR ARRAY. , 1982 .

[19]  Israel Koren.  A reconfigurable and fault-tolerant VLSI multiprocessor array , 1981, ISCA '81.