RTL Assertion Mining with Automated RTL-to-TLM Abstraction

We present a three-step flow to improve Assertion-based Verification methodology with integrated RTL-to-TLM abstraction: First, an automatic assertion miner generates a large set of possible assertions from an RTL design. Second, automatic assertion qualification identifies the most interesting assertions from this set. Third, the assertions are abstracted to the transaction level, such that they can be re-used in TLM verification. We show that the proposed flow automatically chooses the best assertions among the ones generated to verify the design components when abstracted from RTL to TLM. Our experimental results indicate that the proposed methodology allows us to re-use the most interesting set at TLM without relying on any time consuming or error-prone manual transformations with a considerable amount of speed up and considerable reduction in the execution time.

[1]  Görschwin Fey,et al.  Design Understanding: From Logic to Specification* , 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[2]  Ilan Beer,et al.  FoCs: Automatic Generation of Simulation Checkers from Formal Specifications , 2000, CAV.

[3]  Rolf Drechsler,et al.  Proving transaction and system-level properties of untimed SystemC TLM designs , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

[4]  Pang-Ning Tan,et al.  Interestingness Measures for Association Patterns : A Perspective , 2000, KDD 2000.

[5]  Jaideep Srivastava,et al.  Selecting the right interestingness measure for association patterns , 2002, KDD.

[6]  Fabio Somenzi,et al.  Dos and don'ts of CTL state coverage estimation , 2003, DAC '03.

[7]  Manuvir Das,et al.  Perracotta: mining temporal API rules from imperfect traces , 2006, ICSE.

[8]  Franco Fummi,et al.  On the reuse of RTL assertions in SystemC TLM verification , 2014, 2014 15th Latin American Test Workshop - LATW.

[9]  Paul Ammann,et al.  Using model checking to generate tests from specifications , 1998, Proceedings Second International Conference on Formal Engineering Methods (Cat.No.98EX241).

[10]  Atsushi Kasuya,et al.  Verification Methodologies in a TLM-to-RTL Design Flow , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[11]  Timothy Kam,et al.  Coverage estimation for symbolic model checking , 1999, DAC '99.

[12]  Rached Tourki,et al.  An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC , 2005, Comput. Electr. Eng..

[13]  Jaan Raik,et al.  From RTL Liveness Assertions to Cost-Effective Hardware Checkers , 2018, 2018 Conference on Design of Circuits and Integrated Systems (DCIS).

[14]  Franco Fummi,et al.  Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions , 2011, IEEE Transactions on Computers.

[15]  Görschwin Fey,et al.  Property mining using dynamic dependency graphs , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[16]  George S. Avrunin,et al.  Patterns in property specifications for finite-state verification , 1999, Proceedings of the 1999 International Conference on Software Engineering (IEEE Cat. No.99CB37002).

[17]  Sofiène Tahar,et al.  Design and verification of SystemC transaction-level models , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Jaan Raik,et al.  An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics , 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

[19]  Orna Grumberg,et al.  "Have I written enough Properties?" - A Method of Comparison between Specification and Implementation , 1999, CHARME.

[20]  Wolfgang Ecker,et al.  Specification Language for Transaction Level Assertions , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

[21]  Shobha Vasudevan,et al.  Mining Hardware Assertions With Guidance From Static Analysis , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Eman El Mandouh,et al.  Automatic generation of hardware design properties from simulation traces , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[23]  Jaan Raik,et al.  Towards Multidimensional Verification: Where Functional Meets Non-Functional , 2018, 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

[24]  Graziano Pravadelli,et al.  Automatic generation of compact formal properties for effective error detection , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[25]  Stephen McCamant,et al.  The Daikon system for dynamic detection of likely invariants , 2007, Sci. Comput. Program..

[26]  Sanjit A. Seshia,et al.  Scalable specification mining for verification and diagnosis , 2010, Design Automation Conference.

[27]  David Tcheng,et al.  GoldMine: Automatic assertion generation using data mining and static analysis , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[28]  Graziano Pravadelli,et al.  On the estimation of assertion interestingness , 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[29]  Zeljko Zilic,et al.  Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring , 2008 .

[30]  Graziano Pravadelli,et al.  Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach , 2015, VLSI-SoC.

[31]  Graziano Pravadelli,et al.  Automatic extraction of assertions from execution traces of behavioural models , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[32]  Graziano Pravadelli,et al.  A-TEAM: Automatic template-based assertion miner , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[33]  Shobha Vasudevan,et al.  Word level feature discovery to enhance quality of assertion mining , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[34]  R. Tourki,et al.  A new synchronization policy between PSL checkers and SystemC designs at transaction level , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

[35]  James R. Larus,et al.  Mining specifications , 2002, POPL '02.

[36]  Franco Fummi,et al.  Properties Incompleteness Evaluation by Functional Verification , 2007, IEEE Transactions on Computers.