Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation

Due to the fast changing wireless communication standards coupled with strict performance constraints, the demand for flexible yet high-performance architectures is increasing. To tackle the flexibility requirement, Software-Defined Radio (SDR) is emerging as an obvious solution, where the underlying hardware implementation is tuned via software layers to the varied standards depending on power-performance and quality requirements leading to adaptable, cognitive radio. To design the hardware architecture for SDR is an interesting challenge, which involves determining the perfect balance of flexibility and performance for the target algorithmic kernels. In this paper, we conduct such a design case study for representatives of two complexity classes of WCDMA channel estimation algorithms. The two algorithms, polynomial channel estimation and weighted multi-slot averaging, differ also significantly in their algorithmic performance, difference which can be exploited in cognitive radio. Furthermore, we propose new design guidelines for highly specialised architectures that provide just enough flexibility to support multiple applications, targeting adaptability, low power and high-performance. Our experiments with various design points show that the resulting architecture meets the performance constraints of WCDMA and offers weak programmability to tune the architecture depending on power/performance constraints of SDR.

[1]  Kees Moerman,et al.  Vector Processing as an Enabler for Software-Defined Radio in Handheld Devices , 2005, EURASIP J. Adv. Signal Process..

[2]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[3]  Rudy Lauwereins,et al.  Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.

[4]  Joseph Mitola Cognitive Radio for Flexible Mobile Multimedia Communications , 2001, Mob. Networks Appl..

[5]  C. John Glossner,et al.  The Sandbridge SB3011 Platform , 2007, EURASIP J. Embed. Syst..

[6]  Srikrishna Bhashyam,et al.  Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers , 2002, J. VLSI Signal Process..

[7]  Rainer Leupers,et al.  Architecture exploration for embedded processors with LISA , 2002 .

[8]  Xiaobo Zhou,et al.  Performance comparisons of channel estimation techniques in multipath fading CDMA , 2004, IEEE Transactions on Wireless Communications.

[9]  Fumiyuki Adachi,et al.  Performance Comparison between Time-Multiplexed Pilot Channel and Parallel Pilot Channel for Coherent Rake Combining in DS-CDMA Mobile Radio , 1998 .

[10]  Hyunseok Lee,et al.  SODA: A Low-power Architecture For Software Radio , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[11]  N. Wehn,et al.  FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding , 2008, 2008 5th International Symposium on Turbo Codes and Related Topics.

[12]  Norbert Wehn,et al.  A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.