Bi-CMOS technology for semi-custom integrated circuits

Technology requirements for (bipolar metal-oxide semiconductor) BiCMOS and semicustom circuit implementations are reviewed. It is proposed that three basic BiCMOS technologies will evolve: high-performance, low cost, and analog-compatible. A first-order estimate of chip and manufacturing costs for BiCMOS suggests a 20-35% increase in die cost. This increase in die costs can only be justified if system performance is improved by 50% or more. A survey of applications indicates that a 50% increase in performance is usually conservative. Significant improvement in I/O speed, ground bounce, clock skew, as well as just internal gate delay is obtained by judicious use of BiCMOS. The availability of high-speed, low-power, high-density ECL SRAMs (emitter-coupled-logic static random-access memories), and upcoming ECL I/O CPUs makes BiCMOS the obvious choice for implementing high-performance ASIC systems.<<ETX>>

[1]  H. Momose,et al.  High Performance 1.0 μm N-Well CMOS/Bipolar Technology , 1983, 1983 Symposium on VLSI Technology. Digest of Technical Papers.

[2]  S. C. Lee,et al.  Bi-CMOS Circuits for High Performance VLSI , 1984, 1984 Symposium on VLSI Technology. Digest of Technical Papers.

[3]  Takashi Hotta,et al.  CMOS/bipolar circuits for 60-MHz digital processing , 1986 .

[4]  F. Ormerod,et al.  A mixed technology gate array with ECL and BiMOS logic on a single chip , 1987, 1987 Symposium on VLSI Circuits.

[5]  C. G. Sodini,et al.  Device design requirements for MOS analog circuits , 1987, 1987 Symposium on VLSI Circuits.

[6]  I. Masuda,et al.  High-speed BiCMOS technology with a buried twin well structure , 1987, IEEE Transactions on Electron Devices.

[7]  A.M. Voshchenkov,et al.  A high speed super self-aligned bipolar-CMOS technology , 1987, 1987 International Electron Devices Meeting.