A limitation of channel length in dynamic memories

Effects of the channel length on the memory retention characteristics of MOS dynamic RAM (dRAM) cell are studied experimentally by evaluating three different n+polysilicon-gate n-channel samples which contain six different channel lengths. A marked decrease of the memory holding time, which results from the subthreshold current, has been observed with decreasing channel length, gate oxide thickness, and substrate doping density in these n-channel samples with n+polysilicon gate. In an n-channel structure with p+polysilicon gate, the surface potential of the channel increases thus suppressing the surface subthreshold current particularly in a device having a thin oxide layer. A p+polysilicon-gate n-channel dRAM cell having an effective channel length of 0.5 µm has been observed to hold its charge up to 96 s at room temperature for the substrate bias of-4 V, while the n+polysilicon-gate n-channel dRAM cell having the same structure exhibits a memory holding time of 6 ms at the same substrate bias voltage. This paper introduces a new dynamic RAM cell, i.e., the p+polysilicon-gate n-channel cell having a buried p+region along the channel and the storage region. This new device having an effective channel length of 0.2 µm has been demonstrated theoretically to show satisfactory retention characteristics. In this very-short-channel structure, the MOS transistor behaves as a MOSSIT. In addition, it has been demonstrated theoretically that the new dynamic RAM cell has the capability of reducing soft errors due to alpha-particle irradiation.