Compiler Techniques for Massive Parallel Architectures

The paper is concerned with the design of massive parallel architectures. It contains an overview of existing compilation techniques. In particular, tools for a mechanical and provably correct design trajectory are described. New results concerning a hierarchical design methodology based on the class of piecewise linear programs are presented.

[1]  Monica S. Lam,et al.  A Loop Transformation Theory and an Algorithm to Maximize Parallelism , 1991, IEEE Trans. Parallel Distributed Syst..

[2]  Ed F. Deprettere,et al.  Processor clustering for the design of optimal fixed-size systolic arrays , 1991, Proceedings of the International Conference on Application Specific Array Processors.

[3]  Jan L. A. van de Snepscheut,et al.  On the design of some systolic algorithms , 1989, JACM.

[4]  J. Annevelink,et al.  HIFI: a functional design system for VLSI processing arrays , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[5]  Glen G. Langdon,et al.  Computer Design , 1982 .

[6]  H. T. Kung,et al.  Systolic Arrays for (VLSI). , 1978 .

[7]  Laurence A. Wolsey,et al.  Integer and Combinatorial Optimization , 1988 .

[8]  Ed F. Deprettere,et al.  A design methodology for fixed-size systolic arrays , 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

[9]  Jang-Ping Sheu,et al.  Partitioning and Mapping Nested Loops on Multiprocessor Systems , 1991, IEEE Trans. Parallel Distributed Syst..

[10]  D J Evans,et al.  Parallel processing , 1986 .

[11]  L. Thiele,et al.  Hierarchical concepts in the design of processor arrays , 1992, CompEuro 1992 Proceedings Computer Systems and Software Engineering.

[12]  Lothar Thiele,et al.  Uniform design of parallel programs for DSP , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[13]  PEIZONG LEE,et al.  Synthesizing Linear Array Algorithms from Nested For Loop Algorithms , 2015, IEEE Trans. Computers.

[14]  D.I. Moldovan,et al.  On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[15]  Jürgen Teich,et al.  Partitioning of processor arrays: a piecewise regular approach , 1993, Integr..

[16]  J. Ramanujam,et al.  Tiling of Iteration Spaces for Multicomputers , 1990, ICPP.

[17]  François Irigoin,et al.  Supernode partitioning , 1988, POPL '88.

[18]  Dan I. Moldovan,et al.  Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays , 1986, IEEE Transactions on Computers.

[19]  Lothar Thiele,et al.  The concepts of COMPAR- a compiler for massively parallel architectures , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[20]  Ed F. Deprettere,et al.  Systolic array implementation of nested loop programs , 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

[21]  V. van Dongen,et al.  Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[22]  Rami G. Melhem,et al.  Synthesizing Non-Uniform Systolic Designs , 1986, ICPP.

[23]  Richard M. Karp,et al.  The Organization of Computations for Uniform Recurrence Equations , 1967, JACM.

[24]  K. Mani Chandy Parallel program design , 1989 .

[25]  MICHAEL VAN SWAAIJ,et al.  Synthesis of ASIC regular arrays for real-time image processing systems , 1991, J. VLSI Signal Process..

[26]  M. Wolfe,et al.  Massive parallelism through program restructuring , 1990, [1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation.

[27]  Lothar Thiele,et al.  On the design of piecewise regular processor arrays , 1989, IEEE International Symposium on Circuits and Systems,.

[28]  Uwe Schwiegelshohn,et al.  Linear Systolic Arrays for Matrix Comutations , 1989, J. Parallel Distributed Comput..

[29]  Thomas Kailath,et al.  Regular iterative algorithms and their implementation on processor arrays , 1988, Proc. IEEE.

[30]  J. Bu,et al.  Systematic design of regular VLSI processor arrays , 1990 .

[31]  Dan I. Moldovan,et al.  ADVIS: A Software Package for the Design of Systolic Arrays , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Lothar Thiele,et al.  On the hierarchical design of VLSI processor arrays , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[33]  Jürgen Teich,et al.  Control generation in the design of processor arrays , 1991, J. VLSI Signal Process..

[34]  Lothar Thiele On the optimization of regular wavefront arrays , 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.

[35]  P. Quinton Automatic synthesis of systolic arrays from uniform recurrent equations , 1984, ISCA 1984.

[36]  Peter R. Cappello,et al.  The SDEF Systolic Programming System , 1987, ICPP.

[37]  Paul M. Chau,et al.  Vlsi Signal Processing II , 1986 .

[38]  Y. Wong,et al.  Broadcast removal in systolic algorithms , 1988, [1988] Proceedings. International Conference on Systolic Arrays.