Power-bandwidth trade-off on TSV array in 3D IC and TSV-RDL junction design challenges
暂无分享,去创建一个
[1] Yusuf Leblebici,et al. Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs , 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.
[2] Junho Lee,et al. High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV) , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[3] Yong Liu,et al. An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects , 2012, IEEE Journal of Solid-State Circuits.
[4] Taigon Song,et al. Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer , 2009, 2009 11th Electronics Packaging Technology Conference.
[5] Kaustav Banerjee,et al. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.
[6] Yong Liu,et al. A compact low-power 3D I/O in 45nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.
[7] Zheng Xu,et al. Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).
[8] Yi Xu,et al. Characterizing the Spread of Correlated Failures in Large Wireless Networks , 2010, 2010 Proceedings IEEE INFOCOM.