Implementation of RSA Cryptosystem with Improved Systolic Array Architecture

In this paper, we propose a kind of improved systolic array architecture for the implementation of RSA cryptosystem. In this architecture, we regard the long adder module as the iterative core, and reuse it. Although we reduce the circuit area highly, we don′t slow down the process speed. The design is expressed in Verilog, and is verified by FPGA.