论文信息 - Graph-Optimization Techniques for IC Layout and Compaction

Graph-Optimization Techniques for IC Layout and Compaction

This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program.

Hiroyuki Watanabe | Gershon Kedem

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