Minimizing power consumption in digital CMOS circuits

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

[1]  José C. Monteiro,et al.  Retiming sequential circuits for low power , 1993, ICCAD.

[2]  A. Ghosh,et al.  Precomputation-based Sequential Logic Optimization For Low Power , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[3]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[4]  Thomas D. Burd.  Low-Power CMOS Library Design Methodology , 1994 .

[5]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[6]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[7]  R. Dianysian,et al.  Systolic Tree-Searched Vector Quantizer for Real-Time Image Compression , .

[8]  Robert W. Brodersen,et al.  A low-voltage CMOS DC-DC converter for a portable battery-operated system , 1994, Proceedings of 1994 Power Electronics Specialist Conference - PESC'94.

[9]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[10]  Keshab K. Parhi,et al.  Algorithm transformation techniques for concurrent processors , 1989, Proc. IEEE.

[11]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[12]  Anantha P. Chandrakasan,et al.  A low power chipset for portable multimedia applications , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[13]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[14]  R. M. Swanson,et al.  Ion-implanted complementary MOS transistors in low-voltage circuits , 1972 .

[15]  Allen Gersho,et al.  Vector quantization and signal compression , 1991, The Kluwer international series in engineering and computer science.

[16]  Marios C. Papaefthymiou,et al.  Precomputation-based sequential logic optimization for low power , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Chi-Ying Tsui,et al.  Technology Decomposition and Mapping Targeting Low Power Dissipation , 1993, 30th ACM/IEEE Design Automation Conference.

[18]  Oscal T.-C. Chen,et al.  VLSI systolic binary tree-searched vector quantizer for image compression , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Sharad Malik,et al.  Technology Mapping for Low Power , 1993, 30th ACM/IEEE Design Automation Conference.

[20]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[22]  Sharad Malik,et al.  Technology Mapping for Low Power , 1993, DAC 1993.

[23]  Jan M. Rabaey,et al.  Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[24]  M. Kinugawa,et al.  Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI , 1990 .

[25]  Kurt Keutzer,et al.  On average power dissipation and random pattern testability of CMOS combinational logic networks , 1992, ICCAD.